1. Field of the Invention
The present invention relates to an interface technology of a semiconductor memory apparatus, and particularly to an input interface circuit.
2. Description of Related Art
The operating speed of the data communication between devices is increasing along with the rapid advancement of high-speed interface technology. In recent years, the operating speed of the data communication between input and output interface circuits of each device exceeds 1 GHz.
Especially in the interface between a synchronous memory and a CPU, the synchronous memory is configured receive a clock signal output from the CPU and a data signal synchronized with the clock signal, and latch the data signal using rising and falling edges of the clock signal.
FIG. 11 illustrates a general input circuit concerning the present invention. An input interface circuit 300 illustrated in FIG. 11 includes input first stage circuits 61 and 63, a clock tree circuit (CTS) 64, a clock tree replica circuit (CTS replica) 62, and latch circuits 65 and 66. FIG. 11 illustrates the configuration to latch the data supplied from DQi using latch circuits 2 and 3. Note that FIG. 12 illustrates a buffer as the input first stage circuits 61 and 63.
FIG. 13 illustrates waveforms of an externally supplied clock signal, data (DQi signal), and internal signals in the input interface circuit 300.
A DDR interface receives the data (DQi signal) having the phase shifted by 90 degrees with respect to the input clock (CLK). Further, as the system of the DDR interface is to latch multiple addresses and data input using clocks of one CLK pin, CLK must be distributed to each address and data.
By distributing CLK, the clock delay (delay added while passing through the CTS 64 illustrated in FIG. 11) indicated by t6 is added to the CLK line. Therefore, in order to normally latch the data using the latch circuits 65 and 66, it is necessary to add the equivalent amount of delay as the delay added to the CLK line (the delay indicated by t7) also to the data (which is the delay added by passing through the CTS replica 62 illustrated in FIG. 11). This is because that the latch circuits 65 and 66 need to ensure sufficient setup characteristics indicated by t8, and the hold characteristics indicated by t9 for rising and falling edges of CLK.
Japanese Unexamined Patent Application Publication No. 2008-71018 discloses a memory interface circuit for latching a data signal of a synchronous memory. FIG. 14 is a block diagram illustrating the memory interface circuit disclosed in Japanese Unexamined Patent Application Publication No. 2008-71018.
In FIG. 14, 211 is a DDR SDRAM, 212 is a DQS signal, 213a and 213b are data signals, 215 is an input buffer, 216 is a delay circuit, 217 is a data latch, 221 is a memory interface circuit, 222 is a read clock generation circuit, 223 is a main state machine, 257 is a data strobe signal, 253 is a read clock, 250 is an oscillation circuit, 260 is a phase comparator, and 262 is a control circuit.
The DDR SDRAM 211 synchronizes with the clock and outputs the DQS signal 212 and the data signal 213. The memory interface circuit 221 can be connected to the DDR-SDRAM 211. The delay circuit 216 delays the clock output from the oscillation circuit 250, and outputs the clock as the read clock 253. The phase comparator 260 measures the phase difference between the received data strobe signal 257 and the read clock 253. The delay circuit 216 adjusts the delay time of the read clock 253 according to the measured phase difference. The data latch 217 synchronizes with the read clock 253 to obtain the data signal 213. Then the memory interface circuit 221 disclosed in Japanese Unexamined Patent Application Publication No. 2008-71018 can perform stable and highly reliable data signal latch operation even under the deterioration and mismatch of the transmission conditions.